SURVEY OF STUCK-AT FAULT MODELS IN VLSI TESTING: METHODS, TOOLS, AND OPTIMIZATION STRATEGIES

Abstract

The addition of continuous improvement of the Very Large-Scale Integration (VLSI) technology has led to improvements in digital systems through the provision of extra performance, reduced size, and energy efficiency. But, due to increased complexity of integration and a decrease in technology nodes, fault detection and diagnosis in VLSI circuits have become a difficult problem. This review paper gives an extensive description of stuck-at fault models, extensions thereof and contemporary testing techniques of VLSI systems. It describes the basic fault modeling principle, single and multiple stuck-at fault models, and the current innovations of simulation methods, memory BIST routines and implementations of test sets of validation. In addition, the concept of artificial intelligence (AI) and machine learning (ML) integration in fault detection, low-power optimization, and hardware security is highly examined. The limits of traditional fault testing and the opportunities of AI-driven frameworks to solve the issues of scalability and diagnostic efficiency are explicitly identified in the comparative analysis of the state-of-the-art methodologies. The purpose of this survey is to fill in the gap between the past models and future fault-tolerant VlSI systems as well as establish future research directions in the field of fault modeling and test automation.